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| Synopsys announced it's AI driven chip being certified on Samsung foundry SF2 process |
Synopsys has announced that its AI-driven digital and analog design flows have been certified on Samsung Foundry's SF2 process, achieving multiple successful test chip tapeouts.
The Synopsys.ai EDA suite powers these reference flows, which enhance performance, power, and area (PPA), boost productivity, and accelerate analog design migration for Samsung's latest Gate-All-Around (GAA) process technologies.
Samsung's SF2 process was optimized using Synopsys' AI-driven Design Technology Co-Optimization (DTCO) solution, delivering superior PPA compared to non-AI optimizations. This success will extend to Samsung's advanced SF1.4 process.
Sanjay Bali, Synopsys VP, stated that the certification and successful tapeouts using Synopsys.ai, combined with proven Synopsys IP, provide designers with a reliable path to achieving their design goals and faster market entry.
Samsung VP Sangyun Kim highlighted that their collaboration validated PPA results using Synopsys' certified digital flow, achieving 12% higher performance, 25% power reduction, and 5% area reduction compared to the base design.
Synopsys and Samsung are closely working on AI-driven flows, including Synopsys DSO.ai for design productivity and PPA optimization, and Synopsys ASO.ai for faster analog design migration. This collaboration has produced a new analog design migration reference flow using Synopsys ASO.ai, facilitating efficient migration of Samsung 8nm analog IPs to the SF2 process.
Synopsys' new design techniques, such as backside routing, local layout effect-aware methodology, and nanosheet cell design, help customers meet their PPA goals on the Samsung SF2 process family. Integrating these techniques with Synopsys' tools enables designers to enhance transistor performance efficiency and density, optimize power consumption, and reduce area by up to 20% for Samsung's SF2Z process technology.
Synopsys IP supports Samsung processes from SF2 to SF14LPU, offering competitive advantages for chipmakers in automotive, mobile, high-performance computing (HPC), and multi-die designs. Standards-compliant, silicon-proven interface IP includes PCIe, DDR, LPDDR, MIPI, USB, and DisplayPort, enabling broad interoperability.
To facilitate multi-die package integration, Synopsys UCIe IP has successfully taped out in SF2 and SF4x and achieved silicon success in SF5A, ensuring robust die-to-die connectivity with low power and latency. Synopsys Foundation IP, including embedded memories, logic libraries, and GPIOs, is also silicon-proven for leading PPA across various Samsung process technologies.
Synopsys and Samsung's collaboration aims to deliver extensive IP for advanced process technologies. Their partnership supports customers in accelerating multi-die design development using Synopsys 3DIC Compiler, which is qualified for Samsung's SF2 process and supports advanced silicon processes, packaging technologies, and the 3DCODE standard.
As an active member of Samsung Foundries' MDI Alliance, Synopsys aids mutual customers in transitioning to 2.5D and 3D advanced packaging designs.
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