Altair Acquires Metrics Design Automation to Enhance 3D-IC Design and Simulation Capabilities

Altair Acquires Metrics Design Automation to Enhance 3D-IC Design and Simulation Capabilities

Altair Acquires Metrics Design Automation to Enhance 3D-IC Design and Simulation Capabilities
Altair Acquires Metrics Design Automation to Enhance 3D-IC Design and Simulation Capabilities
Image credit: Altair Website 

At DAC 2024, Altair showcased its 3D-IC design and SimLab multi-physics modeling and simulation tool. In a significant move to bolster its capabilities, Altair has announced the acquisition of Metrics Design Automation, a Canadian company led by former Cadence Design Systems CEO Joe Costello (1988-1997).

Metrics Design Automation's digital simulator, DSim, is a comprehensive System Verilog and VHDL RTL simulator designed to simulate the engineering behavior of complex assemblies. This acquisition addresses the increasing complexity of chips and systems driven by AI's data and computing demands, the need for low-latency operations, and the intricate designs of chiplets aimed at achieving high performance efficiently in small form factors.

DSim operates on a software-as-a-service (SaaS) business model for functional simulation and design verification. It is intended to integrate with Altair’s Silicon Debug Tools portfolio, which includes StarVision Pro, RTLvision Pro, SpiceVision Pro, and GateVision Pro, for simulation and debugging. According to Altair, this cloud-based business model "has the potential to transform the semiconductor space by making high-caliber EDA design tools much more affordable and accessible for companies looking to aggressively scale out simulations to accelerate design cycles."

The combined tools from Altair and Metrics can run as desktop applications, on company servers, or in the cloud, enabling large regressions with a pay-as-you-go model. This supports System Verilog and VHDL RTL for digital circuits targeting ASICs and FPGAs. Concurrent and scalable simulations significantly reduce traditional design cycle times and costs, making high-performance design tools more accessible and efficient for modern semiconductor development.

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